1. Field of the Invention
The present invention relates to an internal voltage boosting-up circuit, and more particularly to an internal voltage boosting-up circuit that generates an internally boosted voltage in a semiconductor storage device.
2. Background of the Invention
In the past, in order to achieve stable and efficient reading and writing of memory cell data in a semiconductor memory device, an internal voltage boosting circuit was provided to raise the potential on a word line connected to an n-channel MOS transistor of a memory cell to a voltage that is greater than the externally supplied power supply voltage.
FIG. 1 is a block diagram showing the configuration of a general internal voltage boosting-up circuit.
As shown in FIG. 1, a general voltage boosting circuit is formed by an oscillator circuit 1 to which is input an oscillator control signal 1 and which generates a signal having a prescribed frequency, and an boosted voltage generating circuit 4 which inputs the oscillation signal output of the oscillator circuit 2 and outputs a stepped-up voltage VBOOT.
FIG. 4 is a drawing that shows a specification configuration of a boosted voltage generating circuit shown in FIG. 1, provided for the purpose of describing an example of such a circuit in the related art.
As shown in FIG. 4, the boosted voltage generating circuit 4 has two voltage boosting circuits, 6a and 6b.
The first voltage boosting circuit 6a has a delay element D1, to which an oscillator signal 3 is input, the output (node S1) of which is delayed by tD1, an inverter INVL for inverting the output of the delay element D1, an inverter INV2 for inverting the output of the inverter INV1, a capacitance C1, one end of which is connected to the output (node S3) of the inverter INV2, and the other end of which is connected to a node S4, an NMOS transistor N2, the source and gate of which are connected to the power supply VDD, and the drain of which is connected to the node S4, an NMOS transistor N3, the source of which is connected to the power supply VDD, the drain of which is connected to the node S4, and the gate of which is connected to a node S14, an NMOS transistor N4, the source of which is connected to the node S4, the drain of which is connected to a node S6, and the gate of which is connected to the node S14, an NMOS transistor N5, the source of which is connected to the node S4, the drain of which is connected to the voltage boosted line VBOOT, and the gate of which is connected to a node S6, a NAND logic circuit NA1, the oscillator signal 3 and the output of the delay element D1 being connected to the two inputs thereof, an inverter INV3 for inverting the output of the NAND circuit NA1, and a capacitance C2, one end of which is connected to the output of the inverter INV3 (node S5) and the other end of which is connected to the node S6.
The second voltage boosting circuit 6b has exactly the same configuration as the first voltage boosting circuit 6a, with the exception that, whereas the first voltage boosting circuit 6a inputs the oscillator signal 3, the second voltage boosting circuit 6b inputs the inverted oscillator signal /3 (bar 3) from an inverter INV4.
Stated more explicitly, the second voltage boosting circuit 6b has a delay element D2, to which an oscillator signal /3, which is an inverted signal of the oscillation signal 3, is input, the output (node S11) of which is delayed by tD1, an inverter INV5 for inverting the output of the delay element D2, an inverter INV6 for inverting the output of the inverter INV5, a capacitance C3, one end of which is connected to the output (node S13) of the inverter INV6, and the other end of which is connected to a node S14, an NMOS transistor N7, the source and gate of which are connected to the power supply VDD, and the drain of which is connected to the node S14, an NMOS transistor N8, the source of which is connected to the power supply VDD, the drain of which is connected to the node S14, and the gate of which is connected to the node S4, an NMOS transistor N9, the source of which is connected to the node S14, the drain of which is connected to a node S16, and the gate of which is connected to the node S4, an NMOS transistor N10, the source of which is connected to the node S14, the drain of which is connected to the voltage boosted line VBOOT, and the gate of which is connected to the node S16, a NAND logic circuit NA2, the inverted oscillator signal /3 and the output S11 of the delay element D2 being connected to the two inputs thereof, an inverter INV7 for inverting the output of the NAND circuit NA2, and a capacitance C4, one end of which is connected to the output of the inverter INV7 (node S15) and the other end of which is connected to the node S16.
The operation of the voltage boosting circuit 4 shown in FIG. 4 is described below, with reference being made to signal waveform diagrams.
FIG. 5 is a set of potential waveform diagrams for various nodes in the first voltage boosting circuit 6a of a boosted voltage generating circuit 4 according to the related art, as shown in FIG. 4.
As shown in FIG. 5, when the oscillator signal 3 is at the low level (L), because the node S14, which is the gate voltage of the NMOS transistors N3 and N4 is at a voltage of (VDD+.DELTA.VBOOT), the NMOS transistors N3 and N4 are in the on condition at this time, so that the nodes S4 and S6 are at the voltage VDD.
When the oscillator signal 3 changes from the low level to the high level (H), the capacitances C1 and C2 are charged with a delay of tD1, in accordance with the delay element D1, so that the voltage at the nodes S3 and S5 change from ground (GND) to VDD. When this occurs, the nodes S4 and S6, which are the other ends of the capacitances C1 and C2, which are in the floating condition, change by the amount .DELTA. VBOOT, according to the law of stored charges. That is, in the case in which the capacitances C1 and C2 are sufficiently larger than parasitic capacitances at the nodes S4 and S6, .DELTA. VBOOT is approximately equal to the changing voltage VDD.
As a result of the increase in potential at the node S6, the NMOS transistor N5 changes to the on condition, so that a charge is transferred from the node S4 to the stepped-up voltage line VBOOT, the stepped-up voltage line VBOOT being thereby biased by the boosted-up voltage VBOOT.
Thus, in an internal voltage boosting circuit 4 of the past, by repeating the voltage waveforms on the nodes S4 and S6 are repeated, so as to generate the internally stepped-up voltage VBOOT.
Because the potentials on the various nodes of the second voltage boosting circuit 6b is the same as those on the nodes of the first voltage boosting circuit 6a, with the only difference being that the phases are reversed, these will not be explicitly described herein.
With recent increased demand for more compact portable electronic equipment, limitations have been placed on power supplies, and it is additionally required that operation over longer periods of time than in the past be achieved within these power supply limitations.
With this operating environment as a backdrop, there is an even further need for a reduction in the power consumption of semiconductor memory devices.
Accordingly, the present invention was made in consideration of the above-noted drawbacks in the related art, and has as an object the provision of an internal voltage boosting circuit that provides the capacity available in the past, while achieving a reduction in power consumption.